Placement of Linear Arrays

This paper presents a methodology for mapping linear processor arrays onto FPGA components. By taking advantage of regularity and locality properties of these structures, a placement is pre-deened, allowing vendor tools to skip this phase and produce fast and optimized routing. 1 Introduction In many compute intensive applications such as image or signal processing, time is mostly spent in executing loops. Speeding-up these applications leads to hardware implementations which directly beneet from the inherent loop parallelism. The resulting architecture is a regular array, often a systolic array, made of simple processing elements dedicated to eeciently performing the body of the inner loops 1]. The structure can either be uni or bi-dimensional, but in the following we will restrict to linear arrays only. Implementing such nested loops onto FPGA components presents many advantages. First, the regular nature of FPGA component matches perfectly with the architecture we focus on: replication of identical regularly interconnected processing elements. Second, the best uses of FPGA boards (from a performance point of view) have been demonstrated on many compute intensive applications, as illustrated by the numerous applications implemented on the PAM boards 2]. Third, new advanced microprocessor architectures tend to incorporate reconng-urable resources in their data-path. Parallelizing loops on these speciic areas is a very attractive way to eeciently exploit reconngurable computing. Globally, there are three steps as described in 3]: { Parallelization: This step consists in deriving regular array architectures from loop speciications or equivalent formal description such as systems of aane recurrence equations. The ALPHA language, developed at IRISA allows the programmer to explore transformations needed for systematic derivation of regular arrays and for automatic parallelization 4]. { Partitioning: Since the available reconngurable resources may not support the entire array, transformation of the architecture is required : splitting the array into sub-arrays or clustering groups of processing elements. The automating of this task is still ongoing research and is not yet fully resolved.